1. Field of the Invention
The present invention relates to a semiconductor device and a fabrication method thereof, and more particularly, to a semiconductor device having a silicon oxynitride passivation layer and a fabrication method thereof.
2. Description of the Related Art
As a multilayer metallization process has been put to practical use for a semiconductor device, an intermetal dielectric (IMD) film and a passivation layer on top of a wafer become significant. The IMD film should be formed of a material having a low dielectric constant and have an excellent step coverage in order to reduce the parasitic capacitance between metal wiring layers.
The passivation layer is used to prevent physical and chemical damages to a top metal wiring layer during an assembly and packaging process. This passivation layer is formed (i) by depositing a phosphorous (P)-doped oxide, for example, phosphosilicate glass (PSG), at a low temperature by chemical vapor deposition (CVD), (ii) by depositing an oxide by plasma-enhanced CVD (PECVD), or (iii) by depositing a silicon nitride (SiN) by PECVD.
If the passivation layer is formed of PSG, P contained in the PSG reduces stresses and thus cracks, and improves gettering characteristics of the passivation layer against natrium (Na) ions and other metal contaminants. However, a metal layer is susceptible to corrosion or moisture penetration depending on the amount of P contained in the passivation layer.
A PECVD-oxide passivation layer can reduce a mechanical stress and hydrogen content.
A PECVD-silicon nitride passivation layer functions as a barrier against mobile ions like Na ions and moisture and protects a chip from scratching. Yet, the silicon nitride may result in cracks in the passivation layer in a subsequent heat treatment because of its high mechanical stress.
A passivation layer formed of the above materials, namely PSG, PECVD, or PECVD-silicon nitride, should satisfy the following requirements:
(1) the passivation layer should protect a chip from an external environment. That is, it should absorb all external impacts to allow the chip to reliably operate against packaging materials and a severe user environment. As semiconductor technology advances, it is further expected that a bare chip is to be used in a future package. Therefore, this particular requirement for the passivation layer is more impressing;
(2) the passivation layer should also protect a metal wiring layer. That is, it should prevent pattern shift caused by possible metal deformation and stresses during operating devices, especially prevent metal corrosion caused by chemical materials; and
(3) the passivation layer should prevent a signal propagation delay caused by parasitic capacitance since a device line width becomes smaller. That is, it should have a low dielectric constant.
However, formation of a passivation layer of a material having a low dielectric constant results in the decrease of an adhesion strength to an underlying metal wiring layer or IMD layer, and the decrease of an elastic coefficient, and easy moisture penetration. In addition, the dielectric constant of the passivation layer becomes inconsistent with respect to an external environment, in particular, moisture according to the type of film used. Therefore, a high-speed operating device experiences a delay and thus performance deterioration due to the inconsistency of the dielectric constant of the passivation layer.
Therefore, an object of the present invention is to provide a semiconductor device having a passivation layer which exhibits a low dielectric constant and a high moisture resistance.
Another object of the present invention is to provide a method of fabricating a semiconductor device having a passivation layer which exhibits a low dielectric constant and a high moisture resistance.
To achieve the above object, there is provided a semiconductor device having a silicon oxynitride passivation layer and a fabrication method thereof. The passivation layer is formed of a silicon oxynitride having a dielectric constant of 5.0-6.0 and an atomic composition ratio of silicon (25-40%), oxygen (25-40%), and nitrogen (25-40%). Therefore, the passivation layer has a low dielectric constant and is highly moisture-resistant to thereby reduce the parasitic capacitance between metal wiring layers.
Preferably, the passivation layer is formed to a thickness of about 3000 xc3x85.
To achieve another object of the present invention, there is provided a method of fabricating a semiconductor device having a passivation layer. A semiconductor substrate is loaded into a reaction chamber in an atmosphere of silane (SiH4), nitrous oxide (N2O), and ammonia (NH3) gases. Then, a silicon oxynitride passivation layer is deposited on the semiconductor substrate by reacting the gases, so that the passivation layer has a dielectric constant of 5.0-6.0 and an atomic composition ratio of silicon (25-40%), oxygen (25-40%), and nitrogen (25-40%).
Preferably, the flow ratio of             N      2        ⁢    O              SiH      4        +          NH      3      
is between 0.5 and 1.2.
Preferably, the flow rates of the SiH4, N2O, and NH3 gases are 100 to 1000 sccm, 1000 to 5000 sccm, and 1000 to 10000 sccm, respectively.
Preferably, the silicon oxynitride passivation layer is deposited at 250 to 450xc2x0 C.